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| MONDAY, June 7, 2004, 09:00 AM - 05:00 PM | Room: 6C
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| MONDAY TUTORIAL
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| #1 - Getting Your "Cool ASIC" Up to Speed: Practical Techniques and Tools to Achieve Custom Like Performance in a Power-Aware Design Flow
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| Organizer(s): Ruchir Puri
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| Giga-Hertz frequencies are a common feature among leading edge microprocessors while ASIC designs are still hovering at several hundred MHz range. Most of the custom design benefits come from architectural tradeoffs, use of fabrication process with faster devices, advanced circuit families, structured logic, and flexibility to tune individual transistors. However, it is difficult to utilize some of these custom techniques in ASIC designs due to lower cost, and often lower-power constraints. For example, due to heavy emphasis on lowering cost, ASIC designs usually cannot exploit high-performance fabrication processes due to their significantly lower yields. Similarly, advanced circuit techniques such as dynamic logic are not very beneficial in ASIC designs due to their higher power dissipation and clocking overhead. In the absence of these custom techniques, how can a designer get his ASIC anywhere close to speeds achieved by custom designs while still keeping it cool? In this tutorial, we will answer this question by presenting practical techniques and tools that complement a standard ASIC flow in order to achieve performance and power improvement. This tutorial will span a breadth of techniques addressing technology, circuit and methodology issues. The topics will include: theory of power-performance trade-off with gate sizing, multiple-threshold and multiple-oxide cells, leakage vs dynamic power trade-off, advanced circuit design techniques to achieve lower power, logic/physical synthesis and methodology issues in a power-aware high-performance design flow.
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| Speaker(s): | Stephen Kosonocky - IBM Corp., Yorktown Heights, NY
Ruchir Puri - IBM Corp., Yorktown Heights, NY
Leon Stok - IBM Corp., Yorktown Heights, NY
Dennis Sylvester - Univ. of Michigan, Ann Arbor, MI
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